1 ;*****************************************************************************
2 ;* x86inc.asm: x264asm abstraction layer
3 ;*****************************************************************************
4 ;* Copyright (C) 2005-2013 x264 project
6 ;* Authors: Loren Merritt <lorenm@u.washington.edu>
7 ;* Anton Mitrofanov <BugMaster@narod.ru>
8 ;* Fiona Glaser <fiona@x264.com>
9 ;* Henrik Gramner <henrik@gramner.com>
11 ;* Permission to use, copy, modify, and/or distribute this software for any
12 ;* purpose with or without fee is hereby granted, provided that the above
13 ;* copyright notice and this permission notice appear in all copies.
15 ;* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16 ;* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17 ;* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18 ;* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19 ;* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20 ;* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21 ;* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 ;*****************************************************************************
24 ; This is a header file for the x264ASM assembly language, which uses
25 ; NASM/YASM syntax combined with a large number of macros to provide easy
26 ; abstraction between different calling conventions (x86_32, win64, linux64).
27 ; It also has various other useful features to simplify writing the kind of
28 ; DSP functions that are most often used in x264.
30 ; Unlike the rest of x264, this file is available under an ISC license, as it
31 ; has significant usefulness outside of x264 and we want it to be available
32 ; to the largest audience possible. Of course, if you modify it for your own
33 ; purposes to add a new feature, we strongly encourage contributing a patch
34 ; as this feature might be useful for others as well. Send patches or ideas
35 ; to x264-devel@videolan.org .
37 %ifndef private_prefix
38 %define private_prefix x264
42 %define public_prefix private_prefix
48 %ifidn __OUTPUT_FORMAT__,win32
50 %elifidn __OUTPUT_FORMAT__,win64
52 %elifidn __OUTPUT_FORMAT__,x64
60 %define mangle(x) _ %+ x
65 ; aout does not support align=
66 ; NOTE: This section is out of sync with x264, in order to
67 ; keep supporting OS/2.
68 %macro SECTION_RODATA 0-1 16
69 %ifidn __OUTPUT_FORMAT__,aout
72 SECTION .rodata align=%1
76 %macro SECTION_TEXT 0-1 16
77 %ifidn __OUTPUT_FORMAT__,aout
80 SECTION .text align=%1
86 %elif ARCH_X86_64 == 0
87 ; x86_32 doesn't require PIC.
88 ; Some distros prefer shared objects to be PIC, but nothing breaks if
89 ; the code contains a few textrels, so we'll skip that complexity.
102 ; Macros to eliminate most code duplication between x86_32 and x86_64:
103 ; Currently this works only for leaf functions which load all their arguments
104 ; into registers at the start, and make no other use of the stack. Luckily that
105 ; covers most of x264's asm.
108 ; %1 = number of arguments. loads them from stack if needed.
109 ; %2 = number of registers used. pushes callee-saved regs if needed.
110 ; %3 = number of xmm registers used. pushes callee-saved xmm regs if needed.
111 ; %4 = (optional) stack size to be allocated. If not aligned (x86-32 ICC 10.x,
112 ; MSVC or YMM), the stack will be manually aligned (to 16 or 32 bytes),
113 ; and an extra register will be allocated to hold the original stack
114 ; pointer (to not invalidate r0m etc.). To prevent the use of an extra
115 ; register as stack pointer, request a negative stack size.
116 ; %4+/%5+ = list of names to define to registers
117 ; PROLOGUE can also be invoked by adding the same options to cglobal
120 ; cglobal foo, 2,3,0, dst, src, tmp
121 ; declares a function (foo), taking two args (dst and src) and one local variable (tmp)
123 ; TODO Some functions can use some args directly from the stack. If they're the
124 ; last args then you can just not declare them, but if they're in the middle
125 ; we need more flexible macro.
128 ; Pops anything that was pushed by PROLOGUE, and returns.
131 ; Use this instead of RET if it's a branch target.
134 ; rN and rNq are the native-size register holding function argument N
135 ; rNd, rNw, rNb are dword, word, and byte size
136 ; rNh is the high 8 bits of the word size
137 ; rNm is the original location of arg N (a register or on the stack), dword
138 ; rNmp is native size
140 %macro DECLARE_REG 2-3
150 %elif ARCH_X86_64 ; memory
151 %define r%1m [rstk + stack_offset + %3]
152 %define r%1mp qword r %+ %1 %+ m
154 %define r%1m [rstk + stack_offset + %3]
155 %define r%1mp dword r %+ %1 %+ m
160 %macro DECLARE_REG_SIZE 3
176 DECLARE_REG_SIZE ax, al, ah
177 DECLARE_REG_SIZE bx, bl, bh
178 DECLARE_REG_SIZE cx, cl, ch
179 DECLARE_REG_SIZE dx, dl, dh
180 DECLARE_REG_SIZE si, sil, null
181 DECLARE_REG_SIZE di, dil, null
182 DECLARE_REG_SIZE bp, bpl, null
184 ; t# defines for when per-arch register allocation is more complex than just function arguments
186 %macro DECLARE_REG_TMP 1-*
189 CAT_XDEFINE t, %%i, r%1
195 %macro DECLARE_REG_TMP_SIZE 0-*
197 %define t%1q t%1 %+ q
198 %define t%1d t%1 %+ d
199 %define t%1w t%1 %+ w
200 %define t%1h t%1 %+ h
201 %define t%1b t%1 %+ b
206 DECLARE_REG_TMP_SIZE 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14
217 %assign stack_offset stack_offset+gprsize
224 %assign stack_offset stack_offset-gprsize
228 %macro PUSH_IF_USED 1-*
237 %macro POP_IF_USED 1-*
246 %macro LOAD_IF_USED 1-*
249 mov r%1, r %+ %1 %+ mp
258 %assign stack_offset stack_offset+(%2)
265 %assign stack_offset stack_offset-(%2)
275 %macro movsxdifnidn 2
287 %macro DEFINE_ARGS 0-*
291 CAT_UNDEF arg_name %+ %%i, q
292 CAT_UNDEF arg_name %+ %%i, d
293 CAT_UNDEF arg_name %+ %%i, w
294 CAT_UNDEF arg_name %+ %%i, h
295 CAT_UNDEF arg_name %+ %%i, b
296 CAT_UNDEF arg_name %+ %%i, m
297 CAT_UNDEF arg_name %+ %%i, mp
298 CAT_UNDEF arg_name, %%i
303 %xdefine %%stack_offset stack_offset
304 %undef stack_offset ; so that the current value of stack_offset doesn't get baked in by xdefine
307 %xdefine %1q r %+ %%i %+ q
308 %xdefine %1d r %+ %%i %+ d
309 %xdefine %1w r %+ %%i %+ w
310 %xdefine %1h r %+ %%i %+ h
311 %xdefine %1b r %+ %%i %+ b
312 %xdefine %1m r %+ %%i %+ m
313 %xdefine %1mp r %+ %%i %+ mp
314 CAT_XDEFINE arg_name, %%i, %1
318 %xdefine stack_offset %%stack_offset
319 %assign n_arg_names %0
322 %macro ALLOC_STACK 1-2 0 ; stack_size, n_xmm_regs (for win64 only)
325 %assign %%stack_alignment ((mmsize + 15) & ~15)
326 %assign stack_size %1
328 %assign stack_size -stack_size
330 %assign stack_size_padded stack_size
332 %assign stack_size_padded stack_size_padded + 32 ; reserve 32 bytes for shadow space
334 %assign xmm_regs_used %2
335 %if xmm_regs_used > 8
336 %assign stack_size_padded stack_size_padded + (xmm_regs_used-8)*16
340 %if mmsize <= 16 && HAVE_ALIGNED_STACK
341 %assign stack_size_padded stack_size_padded + %%stack_alignment - gprsize - (stack_offset & (%%stack_alignment - 1))
342 SUB rsp, stack_size_padded
344 %assign %%reg_num (regs_used - 1)
345 %xdefine rstk r %+ %%reg_num
346 ; align stack, and save original stack location directly above
347 ; it, i.e. in [rsp+stack_size_padded], so we can restore the
348 ; stack in a single instruction (i.e. mov rsp, rstk or mov
349 ; rsp, [rsp+stack_size_padded])
351 %if %1 < 0 ; need to store rsp on stack
352 sub rsp, gprsize+stack_size_padded
353 and rsp, ~(%%stack_alignment-1)
354 %xdefine rstkm [rsp+stack_size_padded]
356 %else ; can keep rsp in rstk during whole function
357 sub rsp, stack_size_padded
358 and rsp, ~(%%stack_alignment-1)
367 %macro SETUP_STACK_POINTER 1
369 %if %1 != 0 && (HAVE_ALIGNED_STACK == 0 || mmsize == 32)
371 %assign regs_used (regs_used + 1)
372 %elif ARCH_X86_64 && regs_used == num_args && num_args <= 4 + UNIX64 * 2
373 %warning "Stack pointer will overwrite register argument"
379 %macro DEFINE_ARGS_INTERNAL 3+
389 %if WIN64 ; Windows x64 ;=================================================
395 DECLARE_REG 4, R10, 40
396 DECLARE_REG 5, R11, 48
397 DECLARE_REG 6, rax, 56
398 DECLARE_REG 7, rdi, 64
399 DECLARE_REG 8, rsi, 72
400 DECLARE_REG 9, rbx, 80
401 DECLARE_REG 10, rbp, 88
402 DECLARE_REG 11, R12, 96
403 DECLARE_REG 12, R13, 104
404 DECLARE_REG 13, R14, 112
405 DECLARE_REG 14, R15, 120
407 %macro PROLOGUE 2-5+ 0 ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
410 ASSERT regs_used >= num_args
411 SETUP_STACK_POINTER %4
412 ASSERT regs_used <= 15
413 PUSH_IF_USED 7, 8, 9, 10, 11, 12, 13, 14
415 %if mmsize != 8 && stack_size == 0
418 LOAD_IF_USED 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
419 DEFINE_ARGS_INTERNAL %0, %4, %5
422 %macro WIN64_PUSH_XMM 0
423 ; Use the shadow space to store XMM6 and XMM7, the rest needs stack space allocated.
424 %if xmm_regs_used > 6
425 movaps [rstk + stack_offset + 8], xmm6
427 %if xmm_regs_used > 7
428 movaps [rstk + stack_offset + 24], xmm7
430 %if xmm_regs_used > 8
433 movaps [rsp + (%%i-8)*16 + stack_size + 32], xmm %+ %%i
439 %macro WIN64_SPILL_XMM 1
440 %assign xmm_regs_used %1
441 ASSERT xmm_regs_used <= 16
442 %if xmm_regs_used > 8
443 %assign stack_size_padded (xmm_regs_used-8)*16 + (~stack_offset&8) + 32
444 SUB rsp, stack_size_padded
449 %macro WIN64_RESTORE_XMM_INTERNAL 1
451 %if xmm_regs_used > 8
452 %assign %%i xmm_regs_used
455 movaps xmm %+ %%i, [%1 + (%%i-8)*16 + stack_size + 32]
458 %if stack_size_padded > 0
459 %if stack_size > 0 && (mmsize == 32 || HAVE_ALIGNED_STACK == 0)
462 add %1, stack_size_padded
463 %assign %%pad_size stack_size_padded
466 %if xmm_regs_used > 7
467 movaps xmm7, [%1 + stack_offset - %%pad_size + 24]
469 %if xmm_regs_used > 6
470 movaps xmm6, [%1 + stack_offset - %%pad_size + 8]
474 %macro WIN64_RESTORE_XMM 1
475 WIN64_RESTORE_XMM_INTERNAL %1
476 %assign stack_offset (stack_offset-stack_size_padded)
477 %assign xmm_regs_used 0
480 %define has_epilogue regs_used > 7 || xmm_regs_used > 6 || mmsize == 32 || stack_size > 0
483 WIN64_RESTORE_XMM_INTERNAL rsp
484 POP_IF_USED 14, 13, 12, 11, 10, 9, 8, 7
491 %elif ARCH_X86_64 ; *nix x64 ;=============================================
499 DECLARE_REG 6, rax, 8
500 DECLARE_REG 7, R10, 16
501 DECLARE_REG 8, R11, 24
502 DECLARE_REG 9, rbx, 32
503 DECLARE_REG 10, rbp, 40
504 DECLARE_REG 11, R12, 48
505 DECLARE_REG 12, R13, 56
506 DECLARE_REG 13, R14, 64
507 DECLARE_REG 14, R15, 72
509 %macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
512 ASSERT regs_used >= num_args
513 SETUP_STACK_POINTER %4
514 ASSERT regs_used <= 15
515 PUSH_IF_USED 9, 10, 11, 12, 13, 14
517 LOAD_IF_USED 6, 7, 8, 9, 10, 11, 12, 13, 14
518 DEFINE_ARGS_INTERNAL %0, %4, %5
521 %define has_epilogue regs_used > 9 || mmsize == 32 || stack_size > 0
524 %if stack_size_padded > 0
525 %if mmsize == 32 || HAVE_ALIGNED_STACK == 0
528 add rsp, stack_size_padded
531 POP_IF_USED 14, 13, 12, 11, 10, 9
538 %else ; X86_32 ;==============================================================
540 DECLARE_REG 0, eax, 4
541 DECLARE_REG 1, ecx, 8
542 DECLARE_REG 2, edx, 12
543 DECLARE_REG 3, ebx, 16
544 DECLARE_REG 4, esi, 20
545 DECLARE_REG 5, edi, 24
546 DECLARE_REG 6, ebp, 28
549 %macro DECLARE_ARG 1-*
551 %define r%1m [rstk + stack_offset + 4*%1 + 4]
552 %define r%1mp dword r%1m
557 DECLARE_ARG 7, 8, 9, 10, 11, 12, 13, 14
559 %macro PROLOGUE 2-5+ ; #args, #regs, #xmm_regs, [stack_size,] arg_names...
562 ASSERT regs_used >= num_args
569 SETUP_STACK_POINTER %4
570 ASSERT regs_used <= 7
571 PUSH_IF_USED 3, 4, 5, 6
573 LOAD_IF_USED 0, 1, 2, 3, 4, 5, 6
574 DEFINE_ARGS_INTERNAL %0, %4, %5
577 %define has_epilogue regs_used > 3 || mmsize == 32 || stack_size > 0
580 %if stack_size_padded > 0
581 %if mmsize == 32 || HAVE_ALIGNED_STACK == 0
584 add rsp, stack_size_padded
587 POP_IF_USED 6, 5, 4, 3
594 %endif ;======================================================================
597 %macro WIN64_SPILL_XMM 1
599 %macro WIN64_RESTORE_XMM 1
601 %macro WIN64_PUSH_XMM 0
605 ; On AMD cpus <=K10, an ordinary ret is slow if it immediately follows either
606 ; a branch or a branch target. So switch to a 2-byte form of ret in that case.
607 ; We can automatically detect "follows a branch", but not a branch target.
608 ; (SSSE3 is a sufficient condition to know that your cpu doesn't have this problem.)
617 %define last_branch_adr $$
618 %macro AUTO_REP_RET 0
620 times ((last_branch_adr-$)>>31)+1 rep ; times 1 iff $ != last_branch_adr.
621 %elif notcpuflag(ssse3)
622 times ((last_branch_adr-$)>>31)+1 rep
627 %macro BRANCH_INSTR 0-*
632 %xdefine last_branch_adr %%branch_instr
638 BRANCH_INSTR jz, je, jnz, jne, jl, jle, jnl, jnle, jg, jge, jng, jnge, ja, jae, jna, jnae, jb, jbe, jnb, jnbe, jc, jnc, js, jns, jo, jno, jp, jnp
640 %macro TAIL_CALL 2 ; callee, is_nonadjacent
649 ;=============================================================================
650 ; arch-independent part
651 ;=============================================================================
653 %assign function_align 16
656 ; Applies any symbol mangling needed for C linkage, and sets up a define such that
657 ; subsequent uses of the function name automatically refer to the mangled version.
658 ; Appends cpuflags to the function name if cpuflags has been specified.
659 ; The "" empty default parameter is a workaround for nasm, which fails if SUFFIX
660 ; is empty and we call cglobal_internal with just %1 %+ SUFFIX (without %2).
661 %macro cglobal 1-2+ "" ; name, [PROLOGUE args]
662 cglobal_internal 1, %1 %+ SUFFIX, %2
664 %macro cvisible 1-2+ "" ; name, [PROLOGUE args]
665 cglobal_internal 0, %1 %+ SUFFIX, %2
667 %macro cglobal_internal 2-3+
669 %xdefine %%FUNCTION_PREFIX private_prefix
670 %xdefine %%VISIBILITY hidden
672 %xdefine %%FUNCTION_PREFIX public_prefix
673 %xdefine %%VISIBILITY
676 %xdefine %2 mangle(%%FUNCTION_PREFIX %+ _ %+ %2)
677 %xdefine %2.skip_prologue %2 %+ .skip_prologue
678 CAT_XDEFINE cglobaled_, %2, 1
680 %xdefine current_function %2
681 %ifidn __OUTPUT_FORMAT__,elf
682 global %2:function %%VISIBILITY
688 RESET_MM_PERMUTATION ; needed for x86-64, also makes disassembly somewhat nicer
689 %xdefine rstk rsp ; copy of the original stack pointer, used when greater alignment than the known stack alignment is required
690 %assign stack_offset 0 ; stack pointer offset relative to the return address
691 %assign stack_size 0 ; amount of stack space that can be freely used inside a function
692 %assign stack_size_padded 0 ; total amount of allocated stack space, including space for callee-saved xmm registers on WIN64 and alignment padding
693 %assign xmm_regs_used 0 ; number of XMM registers requested, used for dealing with callee-saved registers on WIN64
700 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
701 CAT_XDEFINE cglobaled_, %1, 1
705 ; like cextern, but without the prefix
706 %macro cextern_naked 1
707 %xdefine %1 mangle(%1)
708 CAT_XDEFINE cglobaled_, %1, 1
713 %xdefine %1 mangle(private_prefix %+ _ %+ %1)
714 %ifidn __OUTPUT_FORMAT__,elf
715 global %1:data hidden
722 ; This is needed for ELF, otherwise the GNU linker assumes the stack is
723 ; executable by default.
724 %ifidn __OUTPUT_FORMAT__,elf
725 SECTION .note.GNU-stack noalloc noexec nowrite progbits
730 %assign cpuflags_mmx (1<<0)
731 %assign cpuflags_mmx2 (1<<1) | cpuflags_mmx
732 %assign cpuflags_3dnow (1<<2) | cpuflags_mmx
733 %assign cpuflags_3dnowext (1<<3) | cpuflags_3dnow
734 %assign cpuflags_sse (1<<4) | cpuflags_mmx2
735 %assign cpuflags_sse2 (1<<5) | cpuflags_sse
736 %assign cpuflags_sse2slow (1<<6) | cpuflags_sse2
737 %assign cpuflags_sse3 (1<<7) | cpuflags_sse2
738 %assign cpuflags_ssse3 (1<<8) | cpuflags_sse3
739 %assign cpuflags_sse4 (1<<9) | cpuflags_ssse3
740 %assign cpuflags_sse42 (1<<10)| cpuflags_sse4
741 %assign cpuflags_avx (1<<11)| cpuflags_sse42
742 %assign cpuflags_xop (1<<12)| cpuflags_avx
743 %assign cpuflags_fma4 (1<<13)| cpuflags_avx
744 %assign cpuflags_avx2 (1<<14)| cpuflags_avx
745 %assign cpuflags_fma3 (1<<15)| cpuflags_avx
747 %assign cpuflags_cache32 (1<<16)
748 %assign cpuflags_cache64 (1<<17)
749 %assign cpuflags_slowctz (1<<18)
750 %assign cpuflags_lzcnt (1<<19)
751 %assign cpuflags_aligned (1<<20) ; not a cpu feature, but a function variant
752 %assign cpuflags_atom (1<<21)
753 %assign cpuflags_bmi1 (1<<22)|cpuflags_lzcnt
754 %assign cpuflags_bmi2 (1<<23)|cpuflags_bmi1
756 %define cpuflag(x) ((cpuflags & (cpuflags_ %+ x)) == (cpuflags_ %+ x))
757 %define notcpuflag(x) ((cpuflags & (cpuflags_ %+ x)) != (cpuflags_ %+ x))
759 ; Takes an arbitrary number of cpuflags from the above list.
760 ; All subsequent functions (up to the next INIT_CPUFLAGS) is built for the specified cpu.
761 ; You shouldn't need to invoke this macro directly, it's a subroutine for INIT_MMX &co.
762 %macro INIT_CPUFLAGS 0-*
770 %xdefine cpuname cpuname %+ _%1
774 %assign cpuflags cpuflags | cpuflags_%1
777 %xdefine SUFFIX _ %+ cpuname
780 %assign avx_enabled 1
782 %if (mmsize == 16 && notcpuflag(sse2)) || (mmsize == 32 && notcpuflag(avx2))
785 %define movnta movntps
789 %elif cpuflag(sse3) && notcpuflag(ssse3)
802 ; m# is a simd register of the currently selected size
803 ; xm# is the corresponding xmm register if mmsize >= 16, otherwise the same as m#
804 ; ym# is the corresponding ymm register if mmsize >= 32, otherwise the same as m#
805 ; (All 3 remain in sync through SWAP.)
816 %assign avx_enabled 0
817 %define RESET_MM_PERMUTATION INIT_MMX %1
823 %define movnta movntq
826 CAT_XDEFINE m, %%i, mm %+ %%i
827 CAT_XDEFINE nnmm, %%i, %%i
839 %assign avx_enabled 0
840 %define RESET_MM_PERMUTATION INIT_XMM %1
844 %define num_mmregs 16
849 %define movnta movntdq
852 CAT_XDEFINE m, %%i, xmm %+ %%i
853 CAT_XDEFINE nnxmm, %%i, %%i
859 ; FIXME: INIT_AVX can be replaced by INIT_XMM avx
862 %assign avx_enabled 1
863 %define PALIGNR PALIGNR_SSSE3
864 %define RESET_MM_PERMUTATION INIT_AVX
868 %assign avx_enabled 1
869 %define RESET_MM_PERMUTATION INIT_YMM %1
873 %define num_mmregs 16
878 %define movnta movntdq
881 CAT_XDEFINE m, %%i, ymm %+ %%i
882 CAT_XDEFINE nymm, %%i, %%i
890 %macro DECLARE_MMCAST 1
895 %define xmmxmm%1 xmm%1
896 %define xmmymm%1 xmm%1
898 %define ymmxmm%1 xmm%1
899 %define ymmymm%1 ymm%1
900 %define xm%1 xmm %+ m%1
901 %define ym%1 ymm %+ m%1
910 ; I often want to use macros that permute their arguments. e.g. there's no
911 ; efficient way to implement butterfly or transpose or dct without swapping some
914 ; I would like to not have to manually keep track of the permutations:
915 ; If I insert a permutation in the middle of a function, it should automatically
916 ; change everything that follows. For more complex macros I may also have multiple
917 ; implementations, e.g. the SSE2 and SSSE3 versions may have different permutations.
919 ; Hence these macros. Insert a PERMUTE or some SWAPs at the end of a macro that
920 ; permutes its arguments. It's equivalent to exchanging the contents of the
921 ; registers, except that this way you exchange the register names instead, so it
922 ; doesn't cost any cycles.
924 %macro PERMUTE 2-* ; takes a list of pairs to swap
931 CAT_XDEFINE nn, m%1, %1
936 %macro SWAP 2+ ; swaps a single chain (sometimes more concise than pairs)
937 %ifnum %1 ; SWAP 0, 1, ...
938 SWAP_INTERNAL_NUM %1, %2
939 %else ; SWAP m0, m1, ...
940 SWAP_INTERNAL_NAME %1, %2
944 %macro SWAP_INTERNAL_NUM 2-*
949 CAT_XDEFINE nn, m%1, %1
950 CAT_XDEFINE nn, m%2, %2
955 %macro SWAP_INTERNAL_NAME 2-*
956 %xdefine %%args nn %+ %1
958 %xdefine %%args %%args, nn %+ %2
961 SWAP_INTERNAL_NUM %%args
964 ; If SAVE_MM_PERMUTATION is placed at the end of a function, then any later
965 ; calls to that function will automatically load the permutation, so values can
966 ; be returned in mmregs.
967 %macro SAVE_MM_PERMUTATION 0-1
971 %xdefine %%f current_function %+ _m
975 CAT_XDEFINE %%f, %%i, m %+ %%i
980 %macro LOAD_MM_PERMUTATION 1 ; name to load from
984 CAT_XDEFINE m, %%i, %1_m %+ %%i
985 CAT_XDEFINE nn, m %+ %%i, %%i
991 ; Append cpuflags to the callee's name iff the appended name is known and the plain name isn't
993 call_internal %1 %+ SUFFIX, %1
995 %macro call_internal 2
1003 LOAD_MM_PERMUTATION %%i
1006 ; Substitutions that reduce instruction size but are functionally equivalent
1031 ;=============================================================================
1032 ; AVX abstraction layer
1033 ;=============================================================================
1038 CAT_XDEFINE sizeofmm, i, 8
1040 CAT_XDEFINE sizeofxmm, i, 16
1041 CAT_XDEFINE sizeofymm, i, 32
1046 %macro CHECK_AVX_INSTR_EMU 3-*
1047 %xdefine %%opcode %1
1051 %error non-avx emulation of ``%%opcode'' is not supported
1058 ;%2 == 1 if float, 0 if int
1059 ;%3 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
1060 ;%4 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1062 %macro RUN_AVX_INSTR 5-8+
1064 %assign __sizeofreg sizeof%6
1066 %assign __sizeofreg sizeof%5
1068 %assign __sizeofreg mmsize
1070 %assign __emulate_avx 0
1071 %if avx_enabled && __sizeofreg >= 16
1072 %xdefine __instr v%1
1076 %assign __emulate_avx 1
1085 CHECK_AVX_INSTR_EMU {%1 %5, %6, %7, %8}, %5, %7, %8
1087 CHECK_AVX_INSTR_EMU {%1 %5, %6, %7}, %5, %7
1091 ; 3-operand AVX instructions with a memory arg can only have it in src2,
1092 ; whereas SSE emulation prefers to have it in src1 (i.e. the mov).
1093 ; So, if the instruction is commutative with a memory arg, swap them.
1098 %if __sizeofreg == 8
1112 __instr %5, %6, %7, %8
1123 ;%2 == 1 if float, 0 if int
1124 ;%3 == 1 if non-destructive or 4-operand (xmm, xmm, xmm, imm), 0 otherwise
1125 ;%4 == 1 if commutative (i.e. doesn't matter which src arg is which), 0 if not
1126 %macro AVX_INSTR 1-4 0, 1, 0
1127 %macro %1 1-9 fnord, fnord, fnord, fnord, %1, %2, %3, %4
1129 RUN_AVX_INSTR %6, %7, %8, %9, %1
1131 RUN_AVX_INSTR %6, %7, %8, %9, %1, %2
1133 RUN_AVX_INSTR %6, %7, %8, %9, %1, %2, %3
1135 RUN_AVX_INSTR %6, %7, %8, %9, %1, %2, %3, %4
1137 RUN_AVX_INSTR %6, %7, %8, %9, %1, %2, %3, %4, %5
1142 ; Instructions with both VEX and non-VEX encodings
1143 ; Non-destructive instructions are written without parameters
1144 AVX_INSTR addpd, 1, 0, 1
1145 AVX_INSTR addps, 1, 0, 1
1146 AVX_INSTR addsd, 1, 0, 1
1147 AVX_INSTR addss, 1, 0, 1
1148 AVX_INSTR addsubpd, 1, 0, 0
1149 AVX_INSTR addsubps, 1, 0, 0
1150 AVX_INSTR aesdec, 0, 0, 0
1151 AVX_INSTR aesdeclast, 0, 0, 0
1152 AVX_INSTR aesenc, 0, 0, 0
1153 AVX_INSTR aesenclast, 0, 0, 0
1155 AVX_INSTR aeskeygenassist
1156 AVX_INSTR andnpd, 1, 0, 0
1157 AVX_INSTR andnps, 1, 0, 0
1158 AVX_INSTR andpd, 1, 0, 1
1159 AVX_INSTR andps, 1, 0, 1
1160 AVX_INSTR blendpd, 1, 0, 0
1161 AVX_INSTR blendps, 1, 0, 0
1162 AVX_INSTR blendvpd, 1, 0, 0
1163 AVX_INSTR blendvps, 1, 0, 0
1164 AVX_INSTR cmppd, 1, 1, 0
1165 AVX_INSTR cmpps, 1, 1, 0
1166 AVX_INSTR cmpsd, 1, 1, 0
1167 AVX_INSTR cmpss, 1, 1, 0
1186 AVX_INSTR divpd, 1, 0, 0
1187 AVX_INSTR divps, 1, 0, 0
1188 AVX_INSTR divsd, 1, 0, 0
1189 AVX_INSTR divss, 1, 0, 0
1190 AVX_INSTR dppd, 1, 1, 0
1191 AVX_INSTR dpps, 1, 1, 0
1193 AVX_INSTR haddpd, 1, 0, 0
1194 AVX_INSTR haddps, 1, 0, 0
1195 AVX_INSTR hsubpd, 1, 0, 0
1196 AVX_INSTR hsubps, 1, 0, 0
1197 AVX_INSTR insertps, 1, 1, 0
1200 AVX_INSTR maskmovdqu
1201 AVX_INSTR maxpd, 1, 0, 1
1202 AVX_INSTR maxps, 1, 0, 1
1203 AVX_INSTR maxsd, 1, 0, 1
1204 AVX_INSTR maxss, 1, 0, 1
1205 AVX_INSTR minpd, 1, 0, 1
1206 AVX_INSTR minps, 1, 0, 1
1207 AVX_INSTR minsd, 1, 0, 1
1208 AVX_INSTR minss, 1, 0, 1
1215 AVX_INSTR movhlps, 1, 0, 0
1216 AVX_INSTR movhpd, 1, 0, 0
1217 AVX_INSTR movhps, 1, 0, 0
1218 AVX_INSTR movlhps, 1, 0, 0
1219 AVX_INSTR movlpd, 1, 0, 0
1220 AVX_INSTR movlps, 1, 0, 0
1228 AVX_INSTR movsd, 1, 0, 0
1231 AVX_INSTR movss, 1, 0, 0
1234 AVX_INSTR mpsadbw, 0, 1, 0
1235 AVX_INSTR mulpd, 1, 0, 1
1236 AVX_INSTR mulps, 1, 0, 1
1237 AVX_INSTR mulsd, 1, 0, 1
1238 AVX_INSTR mulss, 1, 0, 1
1239 AVX_INSTR orpd, 1, 0, 1
1240 AVX_INSTR orps, 1, 0, 1
1244 AVX_INSTR packsswb, 0, 0, 0
1245 AVX_INSTR packssdw, 0, 0, 0
1246 AVX_INSTR packuswb, 0, 0, 0
1247 AVX_INSTR packusdw, 0, 0, 0
1248 AVX_INSTR paddb, 0, 0, 1
1249 AVX_INSTR paddw, 0, 0, 1
1250 AVX_INSTR paddd, 0, 0, 1
1251 AVX_INSTR paddq, 0, 0, 1
1252 AVX_INSTR paddsb, 0, 0, 1
1253 AVX_INSTR paddsw, 0, 0, 1
1254 AVX_INSTR paddusb, 0, 0, 1
1255 AVX_INSTR paddusw, 0, 0, 1
1256 AVX_INSTR palignr, 0, 1, 0
1257 AVX_INSTR pand, 0, 0, 1
1258 AVX_INSTR pandn, 0, 0, 0
1259 AVX_INSTR pavgb, 0, 0, 1
1260 AVX_INSTR pavgw, 0, 0, 1
1261 AVX_INSTR pblendvb, 0, 0, 0
1262 AVX_INSTR pblendw, 0, 1, 0
1263 AVX_INSTR pclmulqdq, 0, 1, 0
1268 AVX_INSTR pcmpeqb, 0, 0, 1
1269 AVX_INSTR pcmpeqw, 0, 0, 1
1270 AVX_INSTR pcmpeqd, 0, 0, 1
1271 AVX_INSTR pcmpeqq, 0, 0, 1
1272 AVX_INSTR pcmpgtb, 0, 0, 0
1273 AVX_INSTR pcmpgtw, 0, 0, 0
1274 AVX_INSTR pcmpgtd, 0, 0, 0
1275 AVX_INSTR pcmpgtq, 0, 0, 0
1280 AVX_INSTR phaddw, 0, 0, 0
1281 AVX_INSTR phaddd, 0, 0, 0
1282 AVX_INSTR phaddsw, 0, 0, 0
1283 AVX_INSTR phminposuw
1284 AVX_INSTR phsubw, 0, 0, 0
1285 AVX_INSTR phsubd, 0, 0, 0
1286 AVX_INSTR phsubsw, 0, 0, 0
1287 AVX_INSTR pinsrb, 0, 1, 0
1288 AVX_INSTR pinsrd, 0, 1, 0
1289 AVX_INSTR pinsrq, 0, 1, 0
1290 AVX_INSTR pinsrw, 0, 1, 0
1291 AVX_INSTR pmaddwd, 0, 0, 1
1292 AVX_INSTR pmaddubsw, 0, 0, 0
1293 AVX_INSTR pmaxsb, 0, 0, 1
1294 AVX_INSTR pmaxsw, 0, 0, 1
1295 AVX_INSTR pmaxsd, 0, 0, 1
1296 AVX_INSTR pmaxub, 0, 0, 1
1297 AVX_INSTR pmaxuw, 0, 0, 1
1298 AVX_INSTR pmaxud, 0, 0, 1
1299 AVX_INSTR pminsb, 0, 0, 1
1300 AVX_INSTR pminsw, 0, 0, 1
1301 AVX_INSTR pminsd, 0, 0, 1
1302 AVX_INSTR pminub, 0, 0, 1
1303 AVX_INSTR pminuw, 0, 0, 1
1304 AVX_INSTR pminud, 0, 0, 1
1318 AVX_INSTR pmuldq, 0, 0, 1
1319 AVX_INSTR pmulhrsw, 0, 0, 1
1320 AVX_INSTR pmulhuw, 0, 0, 1
1321 AVX_INSTR pmulhw, 0, 0, 1
1322 AVX_INSTR pmullw, 0, 0, 1
1323 AVX_INSTR pmulld, 0, 0, 1
1324 AVX_INSTR pmuludq, 0, 0, 1
1325 AVX_INSTR por, 0, 0, 1
1326 AVX_INSTR psadbw, 0, 0, 1
1327 AVX_INSTR pshufb, 0, 0, 0
1331 AVX_INSTR psignb, 0, 0, 0
1332 AVX_INSTR psignw, 0, 0, 0
1333 AVX_INSTR psignd, 0, 0, 0
1334 AVX_INSTR psllw, 0, 0, 0
1335 AVX_INSTR pslld, 0, 0, 0
1336 AVX_INSTR psllq, 0, 0, 0
1337 AVX_INSTR pslldq, 0, 0, 0
1338 AVX_INSTR psraw, 0, 0, 0
1339 AVX_INSTR psrad, 0, 0, 0
1340 AVX_INSTR psrlw, 0, 0, 0
1341 AVX_INSTR psrld, 0, 0, 0
1342 AVX_INSTR psrlq, 0, 0, 0
1343 AVX_INSTR psrldq, 0, 0, 0
1344 AVX_INSTR psubb, 0, 0, 0
1345 AVX_INSTR psubw, 0, 0, 0
1346 AVX_INSTR psubd, 0, 0, 0
1347 AVX_INSTR psubq, 0, 0, 0
1348 AVX_INSTR psubsb, 0, 0, 0
1349 AVX_INSTR psubsw, 0, 0, 0
1350 AVX_INSTR psubusb, 0, 0, 0
1351 AVX_INSTR psubusw, 0, 0, 0
1353 AVX_INSTR punpckhbw, 0, 0, 0
1354 AVX_INSTR punpckhwd, 0, 0, 0
1355 AVX_INSTR punpckhdq, 0, 0, 0
1356 AVX_INSTR punpckhqdq, 0, 0, 0
1357 AVX_INSTR punpcklbw, 0, 0, 0
1358 AVX_INSTR punpcklwd, 0, 0, 0
1359 AVX_INSTR punpckldq, 0, 0, 0
1360 AVX_INSTR punpcklqdq, 0, 0, 0
1361 AVX_INSTR pxor, 0, 0, 1
1362 AVX_INSTR rcpps, 1, 0, 0
1363 AVX_INSTR rcpss, 1, 0, 0
1368 AVX_INSTR rsqrtps, 1, 0, 0
1369 AVX_INSTR rsqrtss, 1, 0, 0
1370 AVX_INSTR shufpd, 1, 1, 0
1371 AVX_INSTR shufps, 1, 1, 0
1372 AVX_INSTR sqrtpd, 1, 0, 0
1373 AVX_INSTR sqrtps, 1, 0, 0
1374 AVX_INSTR sqrtsd, 1, 0, 0
1375 AVX_INSTR sqrtss, 1, 0, 0
1377 AVX_INSTR subpd, 1, 0, 0
1378 AVX_INSTR subps, 1, 0, 0
1379 AVX_INSTR subsd, 1, 0, 0
1380 AVX_INSTR subss, 1, 0, 0
1383 AVX_INSTR unpckhpd, 1, 0, 0
1384 AVX_INSTR unpckhps, 1, 0, 0
1385 AVX_INSTR unpcklpd, 1, 0, 0
1386 AVX_INSTR unpcklps, 1, 0, 0
1387 AVX_INSTR xorpd, 1, 0, 1
1388 AVX_INSTR xorps, 1, 0, 1
1390 ; 3DNow instructions, for sharing code between AVX, SSE and 3DN
1391 AVX_INSTR pfadd, 1, 0, 1
1392 AVX_INSTR pfsub, 1, 0, 0
1393 AVX_INSTR pfmul, 1, 0, 1
1395 ; base-4 constants for shuffles
1398 %assign j ((i>>6)&3)*1000 + ((i>>4)&3)*100 + ((i>>2)&3)*10 + (i&3)
1400 CAT_XDEFINE q000, j, i
1402 CAT_XDEFINE q00, j, i
1404 CAT_XDEFINE q0, j, i
1413 ; tzcnt is equivalent to "rep bsf" and is backwards-compatible with bsf.
1414 ; This lets us use tzcnt without bumping the yasm version requirement yet.
1415 %define tzcnt rep bsf
1417 ; convert FMA4 to FMA3 if possible
1419 %macro %1 4-8 %1, %2, %3, %4
1423 v%6 %1, %4, %3 ; %1 = %1 * %3 + %4
1425 v%7 %1, %2, %4 ; %1 = %2 * %1 + %4
1427 v%8 %1, %2, %3 ; %1 = %2 * %3 + %1
1429 %error fma3 emulation of ``%5 %1, %2, %3, %4'' is not supported
1434 FMA4_INSTR fmaddpd, fmadd132pd, fmadd213pd, fmadd231pd
1435 FMA4_INSTR fmaddps, fmadd132ps, fmadd213ps, fmadd231ps
1436 FMA4_INSTR fmaddsd, fmadd132sd, fmadd213sd, fmadd231sd
1437 FMA4_INSTR fmaddss, fmadd132ss, fmadd213ss, fmadd231ss
1439 FMA4_INSTR fmaddsubpd, fmaddsub132pd, fmaddsub213pd, fmaddsub231pd
1440 FMA4_INSTR fmaddsubps, fmaddsub132ps, fmaddsub213ps, fmaddsub231ps
1441 FMA4_INSTR fmsubaddpd, fmsubadd132pd, fmsubadd213pd, fmsubadd231pd
1442 FMA4_INSTR fmsubaddps, fmsubadd132ps, fmsubadd213ps, fmsubadd231ps
1444 FMA4_INSTR fmsubpd, fmsub132pd, fmsub213pd, fmsub231pd
1445 FMA4_INSTR fmsubps, fmsub132ps, fmsub213ps, fmsub231ps
1446 FMA4_INSTR fmsubsd, fmsub132sd, fmsub213sd, fmsub231sd
1447 FMA4_INSTR fmsubss, fmsub132ss, fmsub213ss, fmsub231ss
1449 FMA4_INSTR fnmaddpd, fnmadd132pd, fnmadd213pd, fnmadd231pd
1450 FMA4_INSTR fnmaddps, fnmadd132ps, fnmadd213ps, fnmadd231ps
1451 FMA4_INSTR fnmaddsd, fnmadd132sd, fnmadd213sd, fnmadd231sd
1452 FMA4_INSTR fnmaddss, fnmadd132ss, fnmadd213ss, fnmadd231ss
1454 FMA4_INSTR fnmsubpd, fnmsub132pd, fnmsub213pd, fnmsub231pd
1455 FMA4_INSTR fnmsubps, fnmsub132ps, fnmsub213ps, fnmsub231ps
1456 FMA4_INSTR fnmsubsd, fnmsub132sd, fnmsub213sd, fnmsub231sd
1457 FMA4_INSTR fnmsubss, fnmsub132ss, fnmsub213ss, fnmsub231ss
1459 ; workaround: vpbroadcastq is broken in x86_32 due to a yasm bug
1460 %if ARCH_X86_64 == 0
1461 %macro vpbroadcastq 2