2 * Format Conversion Utils for MIPS
5 * MIPS Technologies, Inc., California.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
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14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the MIPS Technologies, Inc., nor the names of is
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE MIPS TECHNOLOGIES, INC. ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE MIPS TECHNOLOGIES, INC. BE LIABLE
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24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * Author: Zoran Lukic (zoranl@mips.com)
32 * Author: Nedeljko Babic (nbabic@mips.com)
34 * This file is part of FFmpeg.
36 * FFmpeg is free software; you can redistribute it and/or
37 * modify it under the terms of the GNU Lesser General Public
38 * License as published by the Free Software Foundation; either
39 * version 2.1 of the License, or (at your option) any later version.
41 * FFmpeg is distributed in the hope that it will be useful,
42 * but WITHOUT ANY WARRANTY; without even the implied warranty of
43 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
44 * Lesser General Public License for more details.
46 * You should have received a copy of the GNU Lesser General Public
47 * License along with FFmpeg; if not, write to the Free Software
48 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
51 #include "libavcodec/avcodec.h"
52 #include "libavcodec/fmtconvert.h"
56 static void float_to_int16_mips(int16_t *dst
, const float *src
, long len
)
58 const float *src_end
= src
+ len
;
59 int ret0
, ret1
, ret2
, ret3
, ret4
, ret5
, ret6
, ret7
;
60 float src0
, src1
, src2
, src3
, src4
, src5
, src6
, src7
;
63 * loop is 8 times unrolled in assembler in order to achieve better performance
66 "beq %[len], $zero, fti16_end%= \n\t"
68 "lwc1 %[src0], 0(%[src]) \n\t"
69 "lwc1 %[src1], 4(%[src]) \n\t"
70 "lwc1 %[src2], 8(%[src]) \n\t"
71 "lwc1 %[src3], 12(%[src]) \n\t"
72 "cvt.w.s %[src0], %[src0] \n\t"
73 "cvt.w.s %[src1], %[src1] \n\t"
74 "cvt.w.s %[src2], %[src2] \n\t"
75 "cvt.w.s %[src3], %[src3] \n\t"
76 "mfc1 %[ret0], %[src0] \n\t"
77 "mfc1 %[ret1], %[src1] \n\t"
78 "mfc1 %[ret2], %[src2] \n\t"
79 "mfc1 %[ret3], %[src3] \n\t"
80 "lwc1 %[src4], 16(%[src]) \n\t"
81 "lwc1 %[src5], 20(%[src]) \n\t"
82 "lwc1 %[src6], 24(%[src]) \n\t"
83 "lwc1 %[src7], 28(%[src]) \n\t"
84 "cvt.w.s %[src4], %[src4] \n\t"
85 "cvt.w.s %[src5], %[src5] \n\t"
86 "cvt.w.s %[src6], %[src6] \n\t"
87 "cvt.w.s %[src7], %[src7] \n\t"
88 "addiu %[src], 32 \n\t"
89 "shll_s.w %[ret0], %[ret0], 16 \n\t"
90 "shll_s.w %[ret1], %[ret1], 16 \n\t"
91 "shll_s.w %[ret2], %[ret2], 16 \n\t"
92 "shll_s.w %[ret3], %[ret3], 16 \n\t"
93 "srl %[ret0], %[ret0], 16 \n\t"
94 "srl %[ret1], %[ret1], 16 \n\t"
95 "srl %[ret2], %[ret2], 16 \n\t"
96 "srl %[ret3], %[ret3], 16 \n\t"
97 "sh %[ret0], 0(%[dst]) \n\t"
98 "sh %[ret1], 2(%[dst]) \n\t"
99 "sh %[ret2], 4(%[dst]) \n\t"
100 "sh %[ret3], 6(%[dst]) \n\t"
101 "mfc1 %[ret4], %[src4] \n\t"
102 "mfc1 %[ret5], %[src5] \n\t"
103 "mfc1 %[ret6], %[src6] \n\t"
104 "mfc1 %[ret7], %[src7] \n\t"
105 "shll_s.w %[ret4], %[ret4], 16 \n\t"
106 "shll_s.w %[ret5], %[ret5], 16 \n\t"
107 "shll_s.w %[ret6], %[ret6], 16 \n\t"
108 "shll_s.w %[ret7], %[ret7], 16 \n\t"
109 "srl %[ret4], %[ret4], 16 \n\t"
110 "srl %[ret5], %[ret5], 16 \n\t"
111 "srl %[ret6], %[ret6], 16 \n\t"
112 "srl %[ret7], %[ret7], 16 \n\t"
113 "sh %[ret4], 8(%[dst]) \n\t"
114 "sh %[ret5], 10(%[dst]) \n\t"
115 "sh %[ret6], 12(%[dst]) \n\t"
116 "sh %[ret7], 14(%[dst]) \n\t"
117 "addiu %[dst], 16 \n\t"
118 "bne %[src], %[src_end], fti16_lp%= \n\t"
120 : [ret0
]"=&r"(ret0
), [ret1
]"=&r"(ret1
), [ret2
]"=&r"(ret2
), [ret3
]"=&r"(ret3
),
121 [ret4
]"=&r"(ret4
), [ret5
]"=&r"(ret5
), [ret6
]"=&r"(ret6
), [ret7
]"=&r"(ret7
),
122 [src0
]"=&f"(src0
), [src1
]"=&f"(src1
), [src2
]"=&f"(src2
), [src3
]"=&f"(src3
),
123 [src4
]"=&f"(src4
), [src5
]"=&f"(src5
), [src6
]"=&f"(src6
), [src7
]"=&f"(src7
),
124 [src
]"+r"(src
), [dst
]"+r"(dst
)
125 : [src_end
]"r"(src_end
), [len
]"r"(len
)
130 static void float_to_int16_interleave_mips(int16_t *dst
, const float **src
, long len
,
133 int c
, ch2
= channels
<<1;
134 int ret0
, ret1
, ret2
, ret3
, ret4
, ret5
, ret6
, ret7
;
135 float src0
, src1
, src2
, src3
, src4
, src5
, src6
, src7
;
136 int16_t *dst_ptr0
, *dst_ptr1
, *dst_ptr2
, *dst_ptr3
;
137 int16_t *dst_ptr4
, *dst_ptr5
, *dst_ptr6
, *dst_ptr7
;
138 const float *src_ptr
, *src_ptr2
, *src_end
;
141 src_ptr
= &src
[0][0];
142 src_ptr2
= &src
[1][0];
143 src_end
= src_ptr
+ len
;
147 "lwc1 %[src0], 0(%[src_ptr]) \n\t"
148 "lwc1 %[src1], 0(%[src_ptr2]) \n\t"
149 "addiu %[src_ptr], 4 \n\t"
150 "cvt.w.s $f9, %[src0] \n\t"
151 "cvt.w.s $f10, %[src1] \n\t"
152 "mfc1 %[ret0], $f9 \n\t"
153 "mfc1 %[ret1], $f10 \n\t"
154 "shll_s.w %[ret0], %[ret0], 16 \n\t"
155 "shll_s.w %[ret1], %[ret1], 16 \n\t"
156 "addiu %[src_ptr2], 4 \n\t"
157 "srl %[ret0], %[ret0], 16 \n\t"
158 "srl %[ret1], %[ret1], 16 \n\t"
159 "sh %[ret0], 0(%[dst]) \n\t"
160 "sh %[ret1], 2(%[dst]) \n\t"
161 "addiu %[dst], 4 \n\t"
162 "bne %[src_ptr], %[src_end], fti16i2_lp%= \n\t"
163 : [ret0
]"=&r"(ret0
), [ret1
]"=&r"(ret1
),
164 [src0
]"=&f"(src0
), [src1
]"=&f"(src1
),
165 [src_ptr
]"+r"(src_ptr
), [src_ptr2
]"+r"(src_ptr2
),
167 : [src_end
]"r"(src_end
)
171 for (c
= 0; c
< channels
; c
++) {
172 src_ptr
= &src
[c
][0];
174 src_end
= src_ptr
+ len
;
176 * loop is 8 times unrolled in assembler in order to achieve better performance
180 "lwc1 %[src0], 0(%[src_ptr]) \n\t"
181 "lwc1 %[src1], 4(%[src_ptr]) \n\t"
182 "lwc1 %[src2], 8(%[src_ptr]) \n\t"
183 "lwc1 %[src3], 12(%[src_ptr]) \n\t"
184 "cvt.w.s %[src0], %[src0] \n\t"
185 "cvt.w.s %[src1], %[src1] \n\t"
186 "cvt.w.s %[src2], %[src2] \n\t"
187 "cvt.w.s %[src3], %[src3] \n\t"
188 "mfc1 %[ret0], %[src0] \n\t"
189 "mfc1 %[ret1], %[src1] \n\t"
190 "mfc1 %[ret2], %[src2] \n\t"
191 "mfc1 %[ret3], %[src3] \n\t"
192 "lwc1 %[src4], 16(%[src_ptr]) \n\t"
193 "lwc1 %[src5], 20(%[src_ptr]) \n\t"
194 "lwc1 %[src6], 24(%[src_ptr]) \n\t"
195 "lwc1 %[src7], 28(%[src_ptr]) \n\t"
196 "addu %[dst_ptr1], %[dst_ptr0], %[ch2] \n\t"
197 "addu %[dst_ptr2], %[dst_ptr1], %[ch2] \n\t"
198 "addu %[dst_ptr3], %[dst_ptr2], %[ch2] \n\t"
199 "addu %[dst_ptr4], %[dst_ptr3], %[ch2] \n\t"
200 "addu %[dst_ptr5], %[dst_ptr4], %[ch2] \n\t"
201 "addu %[dst_ptr6], %[dst_ptr5], %[ch2] \n\t"
202 "addu %[dst_ptr7], %[dst_ptr6], %[ch2] \n\t"
203 "addiu %[src_ptr], 32 \n\t"
204 "cvt.w.s %[src4], %[src4] \n\t"
205 "cvt.w.s %[src5], %[src5] \n\t"
206 "cvt.w.s %[src6], %[src6] \n\t"
207 "cvt.w.s %[src7], %[src7] \n\t"
208 "shll_s.w %[ret0], %[ret0], 16 \n\t"
209 "shll_s.w %[ret1], %[ret1], 16 \n\t"
210 "shll_s.w %[ret2], %[ret2], 16 \n\t"
211 "shll_s.w %[ret3], %[ret3], 16 \n\t"
212 "srl %[ret0], %[ret0], 16 \n\t"
213 "srl %[ret1], %[ret1], 16 \n\t"
214 "srl %[ret2], %[ret2], 16 \n\t"
215 "srl %[ret3], %[ret3], 16 \n\t"
216 "sh %[ret0], 0(%[dst_ptr0]) \n\t"
217 "sh %[ret1], 0(%[dst_ptr1]) \n\t"
218 "sh %[ret2], 0(%[dst_ptr2]) \n\t"
219 "sh %[ret3], 0(%[dst_ptr3]) \n\t"
220 "mfc1 %[ret4], %[src4] \n\t"
221 "mfc1 %[ret5], %[src5] \n\t"
222 "mfc1 %[ret6], %[src6] \n\t"
223 "mfc1 %[ret7], %[src7] \n\t"
224 "shll_s.w %[ret4], %[ret4], 16 \n\t"
225 "shll_s.w %[ret5], %[ret5], 16 \n\t"
226 "shll_s.w %[ret6], %[ret6], 16 \n\t"
227 "shll_s.w %[ret7], %[ret7], 16 \n\t"
228 "srl %[ret4], %[ret4], 16 \n\t"
229 "srl %[ret5], %[ret5], 16 \n\t"
230 "srl %[ret6], %[ret6], 16 \n\t"
231 "srl %[ret7], %[ret7], 16 \n\t"
232 "sh %[ret4], 0(%[dst_ptr4]) \n\t"
233 "sh %[ret5], 0(%[dst_ptr5]) \n\t"
234 "sh %[ret6], 0(%[dst_ptr6]) \n\t"
235 "sh %[ret7], 0(%[dst_ptr7]) \n\t"
236 "addu %[dst_ptr0], %[dst_ptr7], %[ch2] \n\t"
237 "bne %[src_ptr], %[src_end], fti16i_lp%= \n\t"
238 : [ret0
]"=&r"(ret0
), [ret1
]"=&r"(ret1
), [ret2
]"=&r"(ret2
), [ret3
]"=&r"(ret3
),
239 [ret4
]"=&r"(ret4
), [ret5
]"=&r"(ret5
), [ret6
]"=&r"(ret6
), [ret7
]"=&r"(ret7
),
240 [src0
]"=&f"(src0
), [src1
]"=&f"(src1
), [src2
]"=&f"(src2
), [src3
]"=&f"(src3
),
241 [src4
]"=&f"(src4
), [src5
]"=&f"(src5
), [src6
]"=&f"(src6
), [src7
]"=&f"(src7
),
242 [dst_ptr1
]"=&r"(dst_ptr1
), [dst_ptr2
]"=&r"(dst_ptr2
), [dst_ptr3
]"=&r"(dst_ptr3
),
243 [dst_ptr4
]"=&r"(dst_ptr4
), [dst_ptr5
]"=&r"(dst_ptr5
), [dst_ptr6
]"=&r"(dst_ptr6
),
244 [dst_ptr7
]"=&r"(dst_ptr7
), [dst_ptr0
]"+r"(dst_ptr0
), [src_ptr
]"+r"(src_ptr
)
245 : [ch2
]"r"(ch2
), [src_end
]"r"(src_end
)
251 #endif /* HAVE_MIPSDSPR1 */
253 static void int32_to_float_fmul_scalar_mips(float *dst
, const int *src
,
257 * variables used in inline assembler
259 float temp1
, temp3
, temp5
, temp7
, temp9
, temp11
, temp13
, temp15
;
261 int rpom1
, rpom2
, rpom11
, rpom21
, rpom12
, rpom22
, rpom13
, rpom23
;
262 const int *src_end
= src
+ len
;
264 * loop is 8 times unrolled in assembler in order to achieve better performance
268 "lw %[rpom11], 0(%[src]) \n\t"
269 "lw %[rpom21], 4(%[src]) \n\t"
270 "lw %[rpom1], 8(%[src]) \n\t"
271 "lw %[rpom2], 12(%[src]) \n\t"
272 "mtc1 %[rpom11], %[temp1] \n\t"
273 "mtc1 %[rpom21], %[temp3] \n\t"
274 "mtc1 %[rpom1], %[temp5] \n\t"
275 "mtc1 %[rpom2], %[temp7] \n\t"
277 "lw %[rpom13], 16(%[src]) \n\t"
278 "lw %[rpom23], 20(%[src]) \n\t"
279 "lw %[rpom12], 24(%[src]) \n\t"
280 "lw %[rpom22], 28(%[src]) \n\t"
281 "mtc1 %[rpom13], %[temp9] \n\t"
282 "mtc1 %[rpom23], %[temp11] \n\t"
283 "mtc1 %[rpom12], %[temp13] \n\t"
284 "mtc1 %[rpom22], %[temp15] \n\t"
286 "addiu %[src], 32 \n\t"
287 "cvt.s.w %[temp1], %[temp1] \n\t"
288 "cvt.s.w %[temp3], %[temp3] \n\t"
289 "cvt.s.w %[temp5], %[temp5] \n\t"
290 "cvt.s.w %[temp7], %[temp7] \n\t"
292 "cvt.s.w %[temp9], %[temp9] \n\t"
293 "cvt.s.w %[temp11], %[temp11] \n\t"
294 "cvt.s.w %[temp13], %[temp13] \n\t"
295 "cvt.s.w %[temp15], %[temp15] \n\t"
297 "mul.s %[temp1], %[temp1], %[mul] \n\t"
298 "mul.s %[temp3], %[temp3], %[mul] \n\t"
299 "mul.s %[temp5], %[temp5], %[mul] \n\t"
300 "mul.s %[temp7], %[temp7], %[mul] \n\t"
302 "mul.s %[temp9], %[temp9], %[mul] \n\t"
303 "mul.s %[temp11], %[temp11], %[mul] \n\t"
304 "mul.s %[temp13], %[temp13], %[mul] \n\t"
305 "mul.s %[temp15], %[temp15], %[mul] \n\t"
307 "swc1 %[temp1], 0(%[dst]) \n\t" /*dst[i] = src[i] * mul; */
308 "swc1 %[temp3], 4(%[dst]) \n\t" /*dst[i+1] = src[i+1] * mul;*/
309 "swc1 %[temp5], 8(%[dst]) \n\t" /*dst[i+2] = src[i+2] * mul;*/
310 "swc1 %[temp7], 12(%[dst]) \n\t" /*dst[i+3] = src[i+3] * mul;*/
312 "swc1 %[temp9], 16(%[dst]) \n\t" /*dst[i+4] = src[i+4] * mul;*/
313 "swc1 %[temp11], 20(%[dst]) \n\t" /*dst[i+5] = src[i+5] * mul;*/
314 "swc1 %[temp13], 24(%[dst]) \n\t" /*dst[i+6] = src[i+6] * mul;*/
315 "swc1 %[temp15], 28(%[dst]) \n\t" /*dst[i+7] = src[i+7] * mul;*/
316 "addiu %[dst], 32 \n\t"
317 "bne %[src], %[src_end], i32tf_lp%= \n\t"
318 : [temp1
]"=&f"(temp1
), [temp11
]"=&f"(temp11
),
319 [temp13
]"=&f"(temp13
), [temp15
]"=&f"(temp15
),
320 [temp3
]"=&f"(temp3
), [temp5
]"=&f"(temp5
),
321 [temp7
]"=&f"(temp7
), [temp9
]"=&f"(temp9
),
322 [rpom1
]"=&r"(rpom1
), [rpom2
]"=&r"(rpom2
),
323 [rpom11
]"=&r"(rpom11
), [rpom21
]"=&r"(rpom21
),
324 [rpom12
]"=&r"(rpom12
), [rpom22
]"=&r"(rpom22
),
325 [rpom13
]"=&r"(rpom13
), [rpom23
]"=&r"(rpom23
),
326 [dst
]"+r"(dst
), [src
]"+r"(src
)
327 : [mul
]"f"(mul
), [src_end
]"r"(src_end
)
331 #endif /* HAVE_INLINE_ASM */
333 av_cold
void ff_fmt_convert_init_mips(FmtConvertContext
*c
)
337 c
->float_to_int16_interleave
= float_to_int16_interleave_mips
;
338 c
->float_to_int16
= float_to_int16_mips
;
340 c
->int32_to_float_fmul_scalar
= int32_to_float_fmul_scalar_mips
;